The present invention relates to a method of manufacturing a high-voltage transistor on a semiconductor substrate. The present invention has particular applicability, in manufacturing nonvolatile semiconductor memory devices requiring a high programming voltage.
Conventional nonvolatile semiconductor memories, such as flash electrically erasable programmable read only memories (Flash EEPROMs), typically comprise a floating gate memory cell, which includes a source region, a drain region and a channel region formed in a semiconductor substrate, and a floating gate formed above the substrate between the channel region and a control gate. A voltage differential is created in the cell when a high voltage, such as about 18 volts, is applied to the control gate while the channel region is kept at a low voltage. This voltage difference causes electrons to move from the channel region to the floating gate through a phenomenon known as tunneling, thus charging the floating gate. This movement of electrons is referred to as programming, and the high voltage (i.e., about 18 volts) applied to the control gate is known as the program voltage.
Flash memory systems conventionally comprise a two-dimensional array of floating gate memory cells. The array typically includes several strings, known as NAND strings, of floating gate memory transistors, each transistor coupled to the next transistor in the string by coupling the source of one device to the drain of the next device to form bit lines. A plurality of word lines, perpendicular to the NAND strings, each connect to the control gate of one memory cell of each NAND string.
To supply a program voltage on demand to each of the word lines, a CMOS transistor referred to as a xe2x80x9crow selectorxe2x80x9d is employed at one end of each word line. This row-selecting transistor must be able to handle voltages of about 20 volts or higher. Additionally, in order to attain an acceptable level of performance and reliability, it must exhibit high gated diode breakdown voltage characteristics to avoid junction breakdown, low leakage from drain to source, and a low body effect so that its threshold voltage is not excessively high. Conventional processing techniques require many separate photolithographic masking steps to manufacture this transistor. The large number of masking steps raises the production cost of the Flash memory device and increases the probability of defects in the finished device.
There exists a need for simplified methodology in manufacturing a high voltage, high performance transistor with fewer processing steps, thereby reducing manufacturing costs and increasing production throughput.
An advantage of the present invention is a simplified method of manufacturing a high voltage transistor with a modified field implant blocking mask such that the transistor exhibits high gated diode breakdown voltage, low leakage and low body effect.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises isolating an active area on a main surface of a semiconductor substrate, the active area comprising a first junction between a first source/drain region and a channel region and a second junction between a second source/drain region and the channel region, where the channel region has a predetermined width and separates the first source/drain region and the second source/drain region. The channel region has opposing ends that are not abutting either of the source/drain regions. A field implant blocking mask is provided over the first source/drain region and over the channel region. The field implant blocking mask has a pair of angled notches at the opposing ends of the channel region. The angled notches extend towards the center of the channel region such that the ends of the notches are a predetermined distance from the opposing ends of the channel region. The angled notches are angled with respect to the first junction between the first source/drain region and the channel region. Thus, the angled notches form a first distance between the first junction at the opposing ends of the channel region and a second distance between the first junction and the ends of the angled notches. The second distance is greater than the first distance. Impurities forming the field implant are then implanted into the substrate. The field implant blocking mask can also extend over the second source/drain region with the angled notches forming a first distance between the second junction at the opposing ends of the channel region and a second distance between the second junction and the ends of the angled notches.
Thus, a semiconductor devices if formed with an active region, including the first source/drain region, the second source/drain region, with the channel region therebetween, with a field implant region that surrounds the first source/drain region and the channel region and extends into the channel region from the opposing ends. The field implant extensions extend into the channel region a predetermined distance to form the ends of the extensions. The field implant extensions are angled relative to the junction between the first source/drain region and the channel region. Thus, the semiconductor device has a field implant extension into the channel region that has a first distance from the junction at the opposing ends of the channel region and has a second distance from the junction at the ends of the extensions. The field implant may surround the second source/drain region with the field implant extensions being angled relative to the junction between the second source/drain region and the channel region.